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ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 1 description the ace93c46 /56/66 provides 1024 /2048/4096 bits of serial electrically erasable programmable read only memory (eeprom) organized as 64 /128/256 words of 16 bits each, when the org pin is connected to vcc and 128 /256/512 words of 8 bits each when it i s tied to ground. the ace93c46 /56/66 is available in space - saving 8 - lead pdip, 8 - lead tssop and 8 - lead jedec soic packages. the ace93c46 /56/66 is enabled through the chip select pin (cs), and accessed via a 3 - wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self - timed and no separate erase cycle is required b efore write. the write cycle is only enabled when it is in the erase/write enable state. when cs is brought high following the initiation of a write cycle, the do pin outputs the ready/busy status. features ? low - voltage operation C 1.8 (vcc=1.8 v to 5.5v) ? three - wire serial interface ? 2mhz clock rate(5v) compatibility ? self - timed write cycle (5 ms max) ? high - reliability C endurance: 1 million write cycles data retention: 100 years packaging type dip - 8 sop - 8 tssop - 8 pin configurations pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply org internal organization dc don t connect
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 2 block diagram ace93c46 note: when the org pin is connected to vcc, the x 16 organization is selected. when it is connected to ground, the x 8 organization is selected. if the org pin is left unconnected and the application does not load the input beyond the capa bility of the internal 1 meg ohm pullup, then the x 16 organization is selected.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 3 ace93c 56/66 note: when the org pin is connected to vcc, the x 16 organization is selected. when it is connected to ground, the x 8 organization is selected. if the org pin is left unconnected and the application does not load the input beyond the capabilit y of the internal 1 meg ohm pullup, then the x 16 organization is selected. absolute maximum ratings dc supply voltage - 0.3 to 6.5v input / output voltage gnd - 0.3 to vcc 0.3v operating ambient temperature - 40 to 85 storage temperature - 65 to 150 *n otice : stresses above those listed under absolute maximum ratings may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 4 ordering information ace 93c46 /56/66 xx + x h pin capacitance applicable over recommended operating range from t a =25 , f=1.0mhz,vcc=+1.8v (unless otherwise noted) test conditions symbol max unit conditions output capacitance (do) cout 5 pf vout=0v input capacitance (cs, sk, di) cin 5 pf vin=0v dc characteristics applicable over recommended operating range from : t a = - 40 to +85 , v cc = + 1.8 v to +5.5v, (unless otherwise noted). symbol parameter test condition min typ max units v cc 1 supply voltage 1.8 5.5 v v cc 2 supply voltage 2.7 5.5 v v cc 3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5 .0 v, read at 1.0 mhz write at 1.0mhz 0.2 0.9 2.0 3.0 ma i sb1 standby current v cc = 1.8 v, cs=0v 1.0 a i sb2 standby current v cc = 2.7 v, cs=0v 1.0 a i sb 3 standby current v cc = 5.0 v, cs=0v 1.0 a i li (1) input leakage v in = 0 to v cc 0.1 1.0 a i li (2) input leak age v in = 0 to v cc 2.0 3.0 a i o l output leakage v in = 0 to v cc 0.1 1.0 a v il1(3) input low voltage 2.7v Q vcc Q 5.5v - 0. 3 0.8 v v i h 1(3) input high voltage 2.7v Q vcc Q 5.5v 2.0 vcc+0.3 v v il 2 (3) input low voltage 1.8 v Q vcc Q 2.7 v - 0. 3 vcc+0.3 v v i h2 (3) input high voltage 1.8 v Q vcc Q 2.7 v vcc*0.7 vcc+0.3 v pb - free u : tube t : tape and reel dp : dip - 8 fm : sop - 8 tm : tssop - 8 halogen - free
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 5 symbol parameter test condition min typ max units v ol1 output low voltage 2.7 v Q vcc Q 5.5 v iol=2.1ma ioh= - 0.4ma 2.4 0.4 v v oh1 output high voltage v ol2 output low voltage 1.8 v Q vcc Q 2.7 v iol=0.15ma ioh= - 100ua vcc - 0.2 0.2 v v oh2 output high voltage note: 1. di.cs. sk input pin 2. org input pin 3. vil min and vih max are reference only and are not tested. applicable over recommended operating range from : t a = - 40 to +85 , v cc = + 1. 8 v to + 5.5 v, cl=1ttl gate and 100pf (unless otherwise noted). symbol parameter test condition min typ max units fsx sk clock frequency 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 0 0 0 2 1 0.25 mhz tskh sk high time 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 250 250 1000 ns tskl sk low time 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 250 250 1000 ns tcs minimum cs low time 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5 v 250 250 1000 ns tcss cs setup time relative to sk 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 50 50 200 ns tdis di setup time relative to sk 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 100 100 400 ns tcsh cs hold time relative to sk 0 ns tdih di hold time relative to sk 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 100 100 400 ns
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 6 symbol parameter test condition min typ max units tpd1 output delay to 1 ac test 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 250 250 1000 ns tpd0 output delay to 0 ac test 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 250 250 10 00 ns tsv cs to status valid ac test 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 250 250 1000 ns tdf cs to do in high impedance ac test cs=vil 4.5 Q vcc Q 5.5v 2.7 Q vcc Q 5.5v 1.8v Q vcc Q 5.5v 100 100 400 ns twp write cycle time 1.5 5 ms endurance (1) 5.0v, 25 1m write cycle note: 1. this parameter is characterized and is not 100% tested. functional description the ace93c46 /56/66 is accessed via a simple and versatile three - wire serial communication interface. device operation is controlled by seven instru ctions issued by the host processor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic1) followed by the appropriate op code and the desired memory address location. instruction set for the ace93c46 instruction sb op code address data comments *8 *16 *8 *16 read 1 10 a 6 - a 0 a 5 - a 0 read data stored in memory, at specified address ewen 1 00 11xxxxx 11xxxx write enable must precede all programming modes rease 1 11 a 6 - a 0 a 5 - a 0 erase memory location an - a0 writ e 1 01 a 6 - a 0 a 5 - a 0 d 7 - d 0 d 15 - d 0 writes memory location an - a0 eral 1 00 10xxxxx 10xxxx erases all memory locations. valid only at vcc=4.5v to 5.5v wral 1 00 01xxxxx 01xxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at vcc=4.5v to 5.5v ewds 1 00 00xxxxx 00xxxx disables all programming instructions notes: the x s in the address field represent don t care values and must be clocked.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 7 instruction set for the ace93c56/66 instruction sb op code address data comments *8 *16 *8 *16 read 1 10 a 8 - a 0 a 7 - a 0 read data stored in memory, at specified address ewen 1 00 11xxxxx x 11xxxx xx write enable must precede all programming modes rease 1 11 a 8 - a 0 a 7 - a 0 erase memory location an - a0 write 1 01 a 8 - a 0 a 7 - a 0 d 7 - d 0 d 15 - d 0 writes memory location an - a0 eral 1 00 10xxxxx xx 10xxxx xx erases all memory locations. valid only at vcc=4.5v to 5.5v wral 1 00 01xxxxx xx 01xxxx xx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at vcc=4.5v to 5.5v ewds 1 00 00xxxxx xx 00xxxx xx disables all programmin g instructions notes: the x s in the address field represent don t care values and must be clocked. read (read): the read (read) instruction contains the address code for the memory location to be read. after the instruction and address are decoded, dat a from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic 0) precedes the 8 - or 16 - bit data output string. the a ce 93c56/66 supports sequential read operations. the device will automatically increment the internal address pointer and clock out the next memory location as long as chip select (cs) is held high .in this case ,the dummy bit (logic 0)will not be clocked out between memory locations, thus allowing for a continuous steam of data to be read. erase/write (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable( ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the ewen state, programming remains enabled until an ewds instruction is executed or vcc power is removed from the part. erase (erase ): the erase (erase) instruction programs all bits in the specified memory location to the logical 1 state. the self - timed erase cycle starts once the erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (tcs). a logic 1 at pin do indicates that the selected memory location has been erased, and the part is ready for another instruction.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 8 write (write): the write (write) instruction contains th e 8 or 16 bits of data to be written into the specified memory location. the self - timed programming cycle, twp, starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (tcs). a logic 0 at do indicates that programming is still in progress. a logic 1 indicates that the memory location at the specified address has been written with the data pattern contained in the ins truction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the selftimed programming cycle, twp. erase all (eral): the erase all (eral) instruction programs every bit in the m emory array to the logic 1 state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (tcs). the eral instruction is valid only at vcc = 5.0v 10%. write all (wral): the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 25 0ns (tcs). the wral instruction is valid only at vcc = 5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction disables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds instructions and can be executed at any time. timing diagrams note: this is the minimum sk period. figure 1: synchronous data timing
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 9 organization key for timing diagrams i/o ace93c46 (1k) ace93c56 (2k) ace93c66 (4k) *16 *8 *8 *16 *8 *16 an a5 a6 a8 (1) a7 (2) a8 a7 dn d15 d7 d7 d15 d7 d15 note : 1. a8 is a dont care value ,but the ext ra clock is required. 2. a7 is a dont care value ,but the extra clock is required. figure 2: read timing figure 3: ewen timing figure 4: ewds timing
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 10 figure 5: write timing note: valid onl y at vcc=4.5v to 5.5v figure 6: wral timing (1) figure 7: erase timing note: valid only at vcc=4.5v to 5.5v figure 8: eral timing (1)
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 11 packaging information dip - 8 note: dimensions in millimeters.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 12 packaging information sop - 8 note: dimensions in millimeters.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 13 packaging information t ssop - 8 note: dimensions in millimeters.
ace93c46 .56.66 t hree - wire serial eeprom ver 1. 5 14 notes ace does not assume any responsibility for use as critical components in life suppor t devices or systems without the express written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, o r (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

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